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rev. 1.7 august 2009 www.aosmd.com page 1 of 15 aoz1016 ezbuck? 2a simple buck regulator general description the aoz1016 is a high efficiency, simple to use, 2a buck regulator. the aoz1016 works from a 4.5v to 16v input voltage range, and provides up to 2a of continuous output current with an output voltage adjustable down to 0.8v. the aoz1016 comes in an so-8 package and is rated over a -40c to +85c ambient temperature range. features 4.5v to 16v operating input voltage range 130m ? internal pfet switch for high efficiency: up to 95% internal schottky diode internal soft start output voltage adjustable to 0.8v 2a continuous output current fixed 500khz pwm operation cycle-by-cycle current limit short-circuit protection under voltage lockout output over voltage protection thermal shutdown small size so-8 package applications point of load dc/dc conversion pcie graphics cards set top boxes dvd drives and hdd lcd panels cable modems telecom/networking/datacom equipment typical application figure 1. 3.3v/2a buck regulator lx vin vin vout fb pgnd en from pc comp agnd c4, c622f ceramic r2 r3 20k c 5 1nf c 2 c122f ceramic l14.7h aoz1016 not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 2 of 15 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configurationpin description part number ambient temperature range package environmental aoz1016ai -40c to +85c so-8 rohs AOZ1016AIL green product lxlx en comp 12 3 4 pgnd vin agnd fb so-8 (top view) 87 6 5 pin number pin name pin function 1 pgnd power ground. electrically needs to be connected to agnd. 2v in supply voltage input. when v in rises above the uvlo threshold the device starts up. 3 agnd reference connection for controller section. also used as thermal connection for controller section. electrically needs to be connected to pgnd. 4 fb the fb pin is used to determine the output vo ltage via a resistor divider between the output and gnd. 5 comp external loop compensation pin. 6 en the enable pin is active high. connect en pin to v in if not used. do not leave the en pin floating. 7, 8 lx pwm output connection to inductor . thermal connection for output stage. not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 3 of 15 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. note: 2. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given application depends on the users specific board design. 500khz/38khz oscillator agnd pgnd vin en fb comp lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 pwm comp level shifter + fet driver isen eamp 0.2v + ? + ? + ? + ? + 0.96v frequency foldback comparator over voltage protection comparator + ? parameter rating supply voltage (v in ) 18v lx to agnd -0.3v to v in +0.3v en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2kv parameter rating supply voltage (v in ) 4.5v to 16v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package thermal resistance ( ja ) (2) so-8 87c/w package thermal resistance ( jc ) so-8 30c/w package power dissipation (p d ) @ 25c ambient so-8 1.15w not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 4 of 15 electrical characteristicst a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. (3 ) note: 3. specification in bold indicate an ambient temperature range of -40c to +85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 16 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.003.70 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 1.2v 23 ma i off shutdown supply current v en = 0v 11 0 a v fb feedback voltage 0.782 0.8 0.818 v load regulation 0.5 % line regulation 0.5 % i fb feedback voltage input current 200 na enable v en en input threshold off threshold on threshold 2.0 0.6 v v hys en input hysteresis 160 mv modulator f o frequency 400 500 600 khz d max maximum duty cycle 100 % d min minimum duty cycle 6% error amplifier voltage gain 500 v / v error amplifier transconductance 200 a / v protection i lim current limit 2.5 3.6 a v pr output over-voltage protection threshold off threshold on threshold 960 860 mv t j over-temperature shutdown limit 150 c t ss soft start interval 2.2 ms output stage high-side switch on-resistance v in = 12v v in = 5v 97 166 130200 m ? not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 5 of 15 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. light load (dcm) operation full load (ccm) operation startup to full load full load to turnoff 50% to 100% load transient light load to turnoff 1 s/div 1 s/div 400 s/div 400 s/div 100 s/div 1s/div vin 10v/div vo 1v/div iin 0.5a/div vo ripple io1a 50mv/div /div vin ripple 0.1v/div vo ripple 20mv/div il 1a/div vlx 10v/div vin ripple 0.1v/div vo ripple 20mv/div il 1a/div vlx 10v/div vin 10v/div vo 1v/div iin 0.5a/div vin 5v/div vo 1v/div iin 0.5a/div not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 6 of 15 typical performance characteristics (continued) circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. vo 2v/div il 1a/div vo 2v/div il 1a/div short circuit protection short circuit recovery 100 s/div 1ms/div aoz1016ai efficiency efficiency (v in = 12v) vs. load current derating curves at 5v input 75 80 85 90 95 2.0 2.5 1.5 1.0 0.5 0 3.3v output 3.3v, 5.0v output 1.8v output 5.0v output 8.0v output 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 25 35 45 55 65 75 85 load current (a) ambient temperature (t a ) efficieny (%) output current (i o ) output current (i o ) derating curves at 12v input 2.0 2.5 1.5 1.0 0.5 0 8.0v output 5.0v output 1.8v output 3.3v output 25 35 45 55 65 75 85 ambient temperature (t a ) thermal de-rating curves for so-8 package part under typical input and output condition based on the evaluation board.25 c ambient temperature and natural convection (air speed < 50lfm) unless otherwise specified. not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 7 of 15 detailed description the aoz1016 is a current-mode step down regulator with integrated high side pmos switch and a low side freewheeling schottky diode. it operates from a 4.5v to 16v input voltage range and supplies up to 2a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltages. features include; enable control, power-on reset, input under voltage lockout, fixed internal soft-start and thermal shut down. the aoz1016 is available in an so-8 package. enable and soft start the aoz1016 has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.0v and voltage on en pin is high. in the soft start process, the output voltage is typically ramped to regulation voltage in 2.2ms. the 2.2ms soft start ti me is set internally. the en pin of the aoz1016 is active high. connect the en pin to v in if the enable function is not used. pulling en to ground will disable the aoz1016. do not leave it open. the voltage on the en pin must be above 2.0v to enable the aoz1016. when voltage on en falls below 0.6v, the aoz1016 is disabled. if an application circuit requires the aoz1016 to be disabled, an open drain or open collector circuit should be used to interface to en pin. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the aoz1016 integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is the sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the internal schottky diode to output. the aoz1016 uses a p-channel mosfet as the high side switch. it saves the bootstrap capacitor normally seen in a circuit which is using an nmos switch. it allows 100% turn-on of the upper switch to achieve linear regu- lation mode of operation. the minimum voltage drop from v in to v o is the load current x dc resistance of mosfet + dc resistance of the buck in ductor. it can be calculated by equation below: where; v o_max is the maximum output voltage, v in is the input voltage from 4.5v to 16v, i o is the output current from 0a to 2a, r ds(on) is the on resistance of the internal mosfet, the value is between 97m ? and 200m ? depending on input voltage and junction temperature, and r inductor is the inductor dc resistance. switching frequency the aoz1016 switching frequency is fixed and set by an internal oscillator. the actu al switching frequency could range from 400khz to 600khz due to device variation. output voltag e programming output voltage can be set by feeding back the output to the fb pin with a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 2 and r 3 . usually, a design is started by picking a fixed r 3 value and calculating the required r 2 with equation below. some standard values of r 2 , r 3 for most commonly used output voltage values are listed in table 1. table 1. v o (v) r 2 (k ? ) r 3 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 v o_max v in i o r ds on () r inductor + () C = v o 0.8 1 r 2 r 3 ------ - + ?? ?? ?? = not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 8 of 15 the combination of r 2 and r 3 should be large enough to avoid drawing excessive current from the output, which will cause power loss. since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper pmos and inductor. protection features the aoz1016 has multiple prot ection features to prevent system circuit damage unde r abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for over current protection. since the aoz1016 employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. the cycle by cycle current limit threshold is set between 2.5a and 3.6a. when the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. the inductor current stop rising. the cycle by cycl e current limit protection directly limits inductor peak current. the average induc- tor current is also limited due to the limitation on peak inductor current. when cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreases. the aoz1016 has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. the fb pin voltage is proportional to the output voltage. whenever fb pin voltage is below 0.2v, the short circuit protection circuit is triggered. as a result, the converter is shut down and hiccups at a frequency equal to 1/8 of normal switching frequency. the converter will start up via a soft start once the short circuit condition is resolved. in short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. output over voltage protection (ovp) the aoz1016 monitors the feedback voltage. when the feedback voltage is higher t han 960mv, it immediately turns-off the pmos to protect the output voltage overshoot at fault condition. when feedback voltage is lower than 860mv, the pmos is allowed to turn on in the next cycle. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4v, the converter starts operation. when input voltage falls below 3.7v, the converter will stop switching. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150c. application information the basic aoz1016 application circuit is shown in figure 1. component selection is explained below. input capacitor the input capacitor (c 1 in figure 1) must be connected to the v in pin and pgnd pin of the aoz1016 to maintain steady input voltage and f ilter out the pulsing input current. a small decoupling capacitor (c d in figure 1), usually 1f, should be connected to the v in pin and agnd pin for stable operat ion of the aoz1016. the voltage rating of input capaci tor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equa- tion below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2. it can be seen that when v o is half of v in , c in is under the worst current stre ss. the worst current stress on c in is 0.5 x i o . v in i o fc in ----------------- 1 v o v in -------- - C ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - C ?? ?? ?? = v o v in -------- - m = not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 9 of 15 figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at the worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high ripple current rating. depending on the application circuits, other low esr tantalum capacitors or aluminum electrolytic capacitors may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufacturers is based on a certain device life time. further de-rating may be necessary for practical design requirement. inductor the inductor is used to supply constant current to output when it is driven by a switch ing voltage. for a given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires a larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through the inductor and switches, which results in less conduc tion loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be consid- ered for long term reliability. output ripple voltage specif ication is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, switching fr equency, output capacitor value and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when a low esr ceramic capacitor is used as an output capacitor, the impedance of the capacitor at the switch- ing frequency dominates. output ripple is primarily caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is primarily decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o i l v o fl ---------- - 1 v o v in -------- - C ?? ?? ?? = i lpeak i o i l 2 -------- + = v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- = v o i l esr co = not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 10 of 15 in a buck converter, output capacitor current is continuous. the rms current of the output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple cu rrent rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high , the output capacitor could be overstressed. loop compensation the aoz1016 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the doubl e pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is the dominant pole and can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter close loop transfer function to get the desired gain and phase. several different types of compensation networks can be used for the aoz1016. in most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. the fb pin and the comp pin are the inverting input and the output of the internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c c is compensati on capacitor. the zero given by the external compensation network, capacitor c c (c 5 in figure 1) and resistor r c (r 1 in figure 1), is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where the control loop has unity gain. the crossover frequency is also called the converter bandwidth. generally, a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high due to system stability concern. when de signing the compensation loop, converter stability under all line and load conditions must be considered. usually, it is recommended to set the bandwidth to be less than 1/10 of the switching frequency. the aoz1016 operates at a fixed switching frequency range from 350khz to 600khz. it is recommended to choose a crossover frequency less than 50khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected cr ossover frequency, f c , to calculate r c : where; f c is the desired crossover frequency, v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit transconductance, which is 5.64 a/v. the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = f c 50 khz = r c f c v o v fb ---------- 2 c o g ea g cs ----------------------------- - = c c 1.5 2 r c f p 1 ----------------------------------- = not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 11 of 15 the previous equation above can also be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout consideration in the aoz1016 buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacitors, to the v in pin, to the lx pins, to the filter indu ctor, to the output capacitor and load, and then returns to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the pgnd pin of the aoz1016, to the lx pins of the aoz1016. current flows in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is recommended to connect input capacitor, output capacitor, and pgnd pin of the aoz1016. in the aoz1016 buck regulator circuit, the two major power dissipating components are the aoz1016 and the output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of the inductor can be approxi- mately calculated by output current and dcr of inductor. the actual aoz1016 junction temperature can be calculated with power dissipation in the aoz1016 and thermal impedance from junction to ambient. the maximum junction temperature of the aoz1016 is 150c, which limits the maximu m load current capability. please see the thermal de-rating curves for the maximum load current of the aoz1016 under different ambient temperatures. the thermal performance of the aoz1016 is strongly affected by the pcb layout. extra care should be taken by users during the design process to ensure that the ic will operate under the reco mmended environmental conditions. several layout tips are listed below for the best electronic and thermal performa nce. figure 3 illustrates a single layer pcb layout example as reference. 1. do not use thermal relief connection to the v in and the pgnd pins. pour a maxi mized copper area to the pgnd pin and the v in pin to help thermal dissipation. 2. the input capacitors should be connected as close as possible to the v in and pgnd pins. 3. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. in this case, a decoupling capacitor should be connected between v in and agnd. 4. make the current trace from lx pins to l to c o to the pgnd as short as possible. 5. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , gnd or v out . 6. the two lx pins are connected to the internal pfet drain. they are low resistance thermal conduction path and a noisy switching node. connecting a copper plane to the lx pin to help thermal dissipa- tion. this copper plane should not be too large otherwise switching noise may be coupled to other parts of the circuit. 7. keep sensitive signal traces such as trace connecting fb and comp away from the lx pins. c c c o r l r c --------------------- = p total_loss v in i in v o i o C = p inductor_loss i o 2 r inductor 1.1 = t junction p total_loss p inductor_loss C () = t ambient ++ not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 12 of 15 figure 3. aoz1016 pcb layout so-8 12 34 87 65 vin agnd comp lxlx en fb cout c5 r1 r3 r2 l cin pgnd cd not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 13 of 15 package dimensions, so-8l notes:1. all dimensions are in millimeters. 2. dimensions are inclusive of plating 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1a2 b c d e1 e e hl dimensions in millimeters min. 1.350.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 0 d c l h x 45 7 (4x) b 2.20 5.74 0.80 unit: mm 1.27 a1 a2 a 0.1 gauge plane seating plane 0.25 e 81 e1 e nom. 1.65 ? 1.50 ?? 4.903.90 1.27 bsc 6.00 ?? ? max. 1.750.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8 symbols a a1a2 b c d e1 e e hl dimensions in inches min. 0.0530.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 0 nom. 0.065 ? 0.059 ?? 0.1930.154 0.050 bsc 0.236 ?? ? max. 0.0690.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050 8 not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 14 of 15 tape and reel dimensions so-8 carrier tapeso-8 reel so-8 tape leader/trailer & orientation tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 see note 5 see note 3 see note 3 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ? not recommended for new designs downloaded from: http:///
aoz1016 rev. 1.7 august 2009 www.aosmd.com page 15 of 15 aoz1016 package marking z1016ai fay assembly lot code fab & assembly location year & w eek code w lt part n umber code underscore denotes green product as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems. not recommended for new designs downloaded from: http:///

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